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s5n 894 7x mcu for adsl/cable modem (revision 0.1) may. 23, 2000 samsung electronics proprietary copyright ? 1999-2000 samsung electronics, inc. all rights reserved
s5n8947 (adsl/cable modem mcu) electronics magic team page : 2 samsung electronics contents 1. general descripti on ................................ ................................ ................................ ................................ 4 2. features ................................ ................................ ................................ ................................ .......................... 5 3. functional block descriptions ................................ ................................ ................................ ......... 6 3.1. b lock d iagram ................................ ................................ ................................ ................................ ......... 6 3.2. a rchitecture ................................ ................................ ................................ ................................ ............ 7 3.3. s ystem m anager ................................ ................................ ................................ ................................ ...... 7 3.4. u nified i nstruction /d ata c ache ................................ ................................ ................................ ............ 7 3.5. sar/u topia i nterface ................................ ................................ ................................ .............................. 7 3.6. e thernet mac ................................ ................................ ................................ ................................ .......... 7 3.7. usb c ontroller ................................ ................................ ................................ ................................ ...... 8 3.8. dma c ontroller ................................ ................................ ................................ ................................ ..... 8 3.9. uart (s erial i/o) ................................ ................................ ................................ ................................ ..... 8 3.10. t imers ................................ ................................ ................................ ................................ .................... 8 3.11. p rogrammable i/o ................................ ................................ ................................ ................................ 8 3.12. i nterrupt c ontroller ................................ ................................ ................................ ......................... 8 3.13. i 2 c s erial i nterface ................................ ................................ ................................ ............................. 9 3.14. pll ( for s ystem /usb) ................................ ................................ ................................ .......................... 9 4. pin descriptions ................................ ................................ ................................ ................................ ......... 10 4.1. p in c onfiguration ................................ ................................ ................................ ................................ .. 10 4.2. p in d escriptions ................................ ................................ ................................ ................................ ..... 11 4.3. p in d escriptions with the p in number and p ad type ................................ ................................ ............ 13 5. operation descrip tion ................................ ................................ ................................ .......................... 16 5.1. cpu c ore o verview ................................ ................................ ................................ ............................... 16 5.2. i nstruction s et ................................ ................................ ................................ ................................ ...... 17 5.3. operating states ................................ ................................ ................................ ............................. 17 5.4. operating modes ................................ ................................ ................................ ............................. 18 5.5. registers ................................ ................................ ................................ ................................ ............. 18 5.6. exceptions ................................ ................................ ................................ ................................ .......... 18 6. hardware structur e ................................ ................................ ................................ ............................. 20 6.1. s ystem m anager ................................ ................................ ................................ ................................ .... 20 6.1.3. overview ................................ ................................ ................................ ................................ ......... 20 6.1.4. system manager registers ................................ ................................ ................................ ............... 20 6.1.5. system memory map ................................ ................................ ................................ ....................... 21 6.2. i nstruction / d ata c ache ................................ ................................ ................................ ...................... 23 6.3. i 2 c b us c ontroller ................................ ................................ ................................ ................................ 24 6.4. e thernet c ontroller ................................ ................................ ................................ ............................ 25 6.4.1. block diagram ................................ ................................ ................................ ................................ 25 6.4.2. features and benefits ................................ ................................ ................................ ...................... 25 6.5. sar and u topia i nterface ................................ ................................ ................................ ..................... 27 6.5.1. block diagram ................................ ................................ ................................ ................................ 27 6.5.2. features and benefits ................................ ................................ ................................ ...................... 27 6.6. usb c ontroller ................................ ................................ ................................ ................................ .... 28 6.6.1. block diagram ................................ ................................ ................................ ................................ 28 6.7. dma c ontroller ................................ ................................ ................................ ................................ ... 29 6.8. uart(s erial i/o) ................................ ................................ ................................ ................................ .... 30 6.9. t imers ................................ ................................ ................................ ................................ ...................... 31
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 3 magic team 6.10. i/o p orts ................................ ................................ ................................ ................................ .............. 32 6.11. i nterrupt c ontroller ................................ ................................ ................................ ........................ 33 7. special function registers ................................ ................................ ................................ ................ 34 8. electric characte ristics ................................ ................................ ................................ ................... 37 8.1. ab solute maximum ratings ................................ ................................ ................................ ........ 37 8.2. r ecommended o perating c onditions ................................ ................................ ................................ ... 37 8.3. dc electrical characteristics ................................ ................................ ................................ 38 8.4. a.c e lectrical c haracteristics ................................ ................................ ................................ ........... 39 9. package dimension ................................ ................................ ................................ ................................ .. 48
s5n8947 (adsl/cable modem mcu) electronics magic team page : 4 samsung electronics 1. g eneral d escription s amsung's s5n8947 16/32-bit risc microcontroller is a cost-effective, high-performance microcontroller solution . the s5n8947 is designed as an integrated ethernet controller for use in managed communication hubs and routers. the s5n8947 also provides atm layer sar (segmentation and reassembly) function with utopia interface and the full-rate usb (universal serial bus) function. the s5n8947 is built around an outstanding cpu core: the 16/32-bit arm7tdmi risc processor designed by advanced risc machines, ltd. the arm7tdmi core is a low-power, general purpose, microprocessor macro-cell that was developed for use in application-specific and custom-specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. important peripheral functions including an uart channel, 2-channel gdma, two 32-bit timers, i 2 c bus controller, and p rogrammable i/o ports are supported . built-in logic including an interrupt controller, dram controller, and a controller for rom/sram and flash memory are also supported . the s5n8947 ? s system manager includes an internal 32-bit system bus arbiter and an external memory controller. to reduce total system cost, the s5n8947 offers a unified cache , ethernet controller , sar and usb . most of the on-chip function blocks have been designed using an hdl synthesizer and the s5n8947 has been fully verified in samsung's state-of-the-art asic test environment.
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 5 magic team 2. features 4-kbyte unified cache sar (segmentation and reassembly) utopia (the universal test & operations phy interface for atm) level 2 interface ethernet mac full-rate usb controller 2-ch gdma (general purpose direct memory access) uart (universal asynchronous receiver and transmtter) 2 programmable 32bits timers 18 programmable i/o ports interrupt controller i 2 c controller built-in plls for system/usb cost effective jtag-based debug solution boundary scan operating voltage range(2.5v +/- 0.2v) operating frequency up to 50mhz 208 tqfp package
s5n8947 (adsl/cable modem mcu) electronics magic team page : 6 samsung electronics 3. f unctional b lock d escriptions 3.1. block diagram arm7tdmi 32bit risc cpu ice breaker cpu interface unified cache 4-word write buffer bus router general i/o ports interrupt controller uart 32bit timer 0, 1 gdma 0, 1 memory controller with refresh control system bus arbiter tap controller for jtag 32-bit system bus 4-bank rom sram flash 4-bank dram 4-bank external i/o device external bus master ethernet mac usb interface pll* (usb) x'tal osc sar/utopia connection memory pll* (system) iic controller figure 1 top block diagram
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 7 magic team 3.2. architecture integrated system for embedded ethernet / usb / sar fully 16/32-bit risc architecture efficient and powerful arm7tdmi core little/big-endian mode is supported basically, but the internal architecture is big-endian. cost-effective jtag-based debug solution supports boundary scan 3.3. system manager 8/16/32-bit external bus support for rom/sram, flash memory, dram and external i/o one external bus master with bus request/acknowledge pins supports for edo/normal or sdram programmable access cycle four-word depth write buffer cost-effective memory-to-peripheral dma interface 3.4. unified instruction/data cache two-way set-associative unified cache (4kbytes) supports for lru (least recently used) protocol cache is configurable as internal sram 3.5. sar/utopia interface directly supports atm adaptation layer five (aal5) segmentation and reassembly segments and reassembles data up to 70mbps a glueless utopia level 2 interface is supprted ( for r eceiving and transmitting atm cells with sar, it is a standard atm interface between atm link and physical layer). 3.6. ethernet mac 2 dma engines with burst mode full compliance with ieee standard 802.3 supports mii interface (7-wire 10-mbps interface is also supported).
s5n8947 (adsl/cable modem mcu) electronics magic team page : 8 samsung electronics 3.7. usb controller supports 12mbps full rate function for universal serial bus 3.8. dma controller 2-channel general purpose dma (for memory-to-memory, memory-to-usb, usb-to-memory, uart- to-memeory, memory-to-uart data transfers without cpu intervention) initiated by a software or a external dma request increments or decrements source or destination address in 8-bit, 16-bit or 32-bit data transfers 3.9. uart (serial i/o) uart (serial i/o) block with dma-based or interrupt-based operation supports for 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive programmable baud rates infra-red (ir) tx/rx support (irda) 3.10. timers two programmable 32-bit timers interval mode or toggle mode operation supports a watchdog timer. 3.11. programmable i/o 18 programmable i/o ports pins individually configurable to input, output, or i/o mode for dedicated signals 3.12. interrupt controller 18 interrupt sources, including 4 external interrupt sources normal or fast interrupt mode (irq, fiq) prioritized interrupt handling
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 9 magic team 3.13. i 2 c serial interface single master mode operation only 3.14. pll (for system/usb) the external clock can be multiplied by on-chip plls to provide high frequency system/usb clock the input frequency is fixed to 12 mhz the output frequency is 4.167 times the input clock for system. the output frequency is 4 times the input clock for usb.
s5n8947 (adsl/cable modem mcu) electronics magic team page : 10 samsung electronics 4. pin descriptions 4.1. pin configuration s5n8947 208-tqfp-2828 (top view) vdd vss osc_xin osc_xo xclk_i vss filter_s vdda_s vssa_s filter_u vdda_u vssa_u ntrst tdi tdo tms tck clkoen mclko vdd vss nreset b0size[0] b0size[1] extmreq extmack bigend ndtack noe necs[0] necs[1] necs[2] necs[3] nrcs[0] vdd vss nrcs[1] nrcs[2] nrcs[3] nras[0] nras[1] nras[2] nras[3] ncas[0] ncas[1] ncas[2] ncas[3] ndwe nwbe[0] nwbe[1] vdd vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 vss vdd xdata[19] xdata[18] xdata[17] xdata[16] xdata[15] xdata[14] xdata[13] xdata[12] xdata[11] xdata[10] xdata[9] xdata[8] xdata[7] xdata[6] vss vdd xdata[5] xdata[4] xdata[3] xdata[2] xdata[1] xdata[0] addr[21] addr[20] addr[19] addr[18] addr[17] addr[16] addr[15] addr[14] addr[13] vss vdd addr[12] addr[11] addr[10] addr[9] addr[8] addr[7] addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] nwbe[3] nwbe[2] vss vdd 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 vss vdd uto_txclav uto_txenb uto_txsoc uto_txd[7] uto_txd[6] uto_txd[5] uto_txd[4] uto_txd[3] uto_txd[2] uto_txd[1] uto_txd[0] uto_txadr[2] uto_txadr[1] uto_txadr[0] vss vdd pp[17] pp[16] pp[15] pp[14] pp[13] pp[12] pp[11] pp[10] pp[9] pp[8] pp[7] pp[6] pp[5] pp[4] pp[3] vss vdd pp[2] pp[1] pp[0] xdata[31] xdata[30] xdata[29] xdata[28] xdata[27] xdata[26] xdata[25] xdata[24] xdata[23] xdata[22] xdata[21] xdata[20] vss vdd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 vdd vss uto_rxadr[0] uto_rxadr[1] uto_rxadr[2] uto_rxd[0] uto_rxd[1] uto_rxd[2] uto_rxd[3] uto_rxd[4] uto_rxd[5] uto_rxd[6] uto_rxd[7] uto_rxsoc uto_rxenb uto_rxclav uto_clk vdd vss scl sda uclk uarxd uatxd nuadtr nuadsr mdc mdio col rxd[0] rxd[1] rxd[2] rxd[3] rx_dv vdd vss rx_clk rx_err tx_clk txd[0] txd[1] txd[2] txd[3] tx_en tx_err crs usb_dp usb_dn tmode clksel vdd vss 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 figure 2 s5n8947 pin configuration
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 11 magic team 4.2. pin descriptions group pin name pin counts i/o type description xclk _i 1 i external system clock source input. mclko 1 o system clock out. clksel 1 i clock frequency select from the internal pll. nreset 1 i system reset, low active. clkoen 1 i system clock out enable. bigend 1 i big endian mode select pin. filter_s 1 o pll filter pin for system clock generation. osc_xin 1 i 12mhz reference clock. system configurations (9) osc_xo 1 o crystal clock output. tmode 1 i test mode enable . tck 1 i jtag test clock input. tms 1 i jtag test mode select. tdi 1 i jtag test data input. tdo 1 o jtag test data output. tap control (5) ntrst 1 i jtag reset signal, low active. addr[21:0] 22 o address bus. xdata[31:0] 32 i/o external bidirectional 32bit data bus. nras[3:0] 4 o row addresssstrobe for dram, low active. ncas[3:0] 4 o column address strobe for dram, low active. ndwe 1 o write enable, low active. necs[3:0] 4 i/o external i/o select, low active. ndtack 1 i external data acknowledge signal. nrcs[3:0] 4 o rom/sram/flash chip select, low active. b0size[1:0] 2 i bank 0 data bus size for boot rom. noe 1 o output enable, low active. nwbe[3:0] 4 o write byte enable, low active. extmreq 1 i external master bus request. memory interface (81) extmack 1 o external bus acknowledge. mcd 1 o management data clock. mdio 1 i/ o management data i/o. col/col_10m 1 i collision detected/collision detected for 10m. tx_clk/ tx_clk_10m 1 i transmit clk/transmit clk for 10m. txd[3:0]/ txd_10m/ loop_10m 4 o transmit data/transmit data for 10m. tx_en/ txen_10m 1 o transmit enable/transmit enable for 10m. tx_err/ pcomp_10m 1 o transmit error/packet compression enable for 10m. crs/crs_10m 1 i carrier sense/carrier sense for 10m. rx_clk/ rxclk_10m 1 i receive clock/receive clock for 10m. rxd[3:0]/ rxd_10m 4 i receive data/receive data for 10m. rx_dv/ link_10m 1 i receive data valid. ethernet controller (18) rx_err 1 i receive error. uclk 1 i external clock input for uart. uarxd 1 i uart receive data. uart (5) uatxd 1 o uart transmit data.
s5n8947 (adsl/cable modem mcu) electronics magic team page : 12 samsung electronics nuadtr 1 i uart data terminal ready, low active. nuadsr 1 o uart data set ready, low active. p[7:0] 8 i/o general i/o ports for bi-directional data only. xintreq[3:0] /p[11:8] 4 i/o external interrupt requests/general i/o ports. xdreq[1:0]/ p[13:12] 2 i/o external dma requests for gdma/general i/o ports. nxdack[1:0]/ p[15:14] 2 i/o external dma acknowledge from gdma/general i/o ports. timer0/ p[16] 1 i/o timer0 out/general i/o port. general purpose in/out ports (including xintreq nxdreq nxdack timer0,1) (18) timer1/ p[17] 1 i/o timer1 out /general i/o port. scl 1 i/o i 2 c serial clock. i 2 c (2) sda 1 i/o i 2 c seral data. uto_tx a d r[2:0] 3 o transmit address bus. uto_txd[7:0] 8 o transmit data bus to the atm phy. uto_txsoc 1 o start of cell indicator for transmit data. uto_txenb 1 o transmit data transfer enable, low active. uto_txcl av 1 i cell buffer available for transmit data. uto_txadr[2:0] 3 o receive address bus. uto_rxd [7:0] 8 i receive data bus from the atm phy. uto_rxsoc 1 i start of cell indicator for receive data. uto_rxenb 1 o receive data transfer enable, low active. uto_rxclav 1 i cell buffer available for receive data. utopia (level 2) (30) uto_clk 1 o transfer/receive interface byte clock. usb_dp 1 i/o usb data d+ usb_dn 1 i/o usb data d- usb (3) filter_u 1 o usb pll filter pin. table 1 signal pin descriptions for each group
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 13 magic team 4.3. pin descriptions with the pin number and pad type pin no pin name i/o type pad type descriptions 1 vdd 2 vss 3 osc_xin i 12mhz reference clock 4 osc_xo o psoscm2 usb crystal clock out 5 xclk_i i ptic s5n8947 system source clock 6 vss 7 filter_s o poa_bb system pll filter pin 8 vdda_s pwr vdda analog power for pll 9 vssa/vbba_s gnd vbba analog / bulk ground for pll 10 filter_u o poa_bb usb pll filter pin 11 vdda_u pwr vdda analog power for pll 12 vssa/vbba_u gnd vssa analog / bulk ground for pll 13 ntrst i pticu jtag not reset 14 tdi i pticu jtag test data in 15 tdo o ptot2 jtag test data out 16 tms i pticu jtag test mode select 17 tck i ptic jtag test clock 18 clkoen i ptic clock out enable/disable 19 mclko o pob8 system clock out 20 vdd pwr 21 vss gnd 22 nreset i ptis not reset 23-24 b0size[0:1] i ptic bank 0 data bus access size 25 extmreq i ptic external master bus request 26 extmack o pob1 external bus acknowledge 27 bigend i pticd big endian mode select pin 28 ndack i ptic not external acknowledge signal 29 noe o ptot4 not output enable 30-33 necs[0:3] b pbct4 not external i/o select 34-39 nrcs[0:3] o ptot4 not rom/sram/flash chip select 40-43 nras[0:3] o ptot4 not row address strobe for dram 44-47 ncas[0:3] o ptot4 not column address strobe for dram 48 ndwe o ptot4 not write enable 49-50 nwbe[0:1] o ptot4 not write byte enable 51 vdd pwr 52 vss gnd 53 vdd pwr 54 vss gnd 55-56 nwbe[2:3] o ptot4 not write byte enable 57-69 addr[0:12] o ptot6 address bus 70 vdd pwr 71 vss gnd 72-80 addr[13:21] o ptot6 address bus 81-86 xdata[0:5] b ptbsut6 external bidirectional data bus 87 vdd pwr 88 vss gnd 89- 102 xdata[6:19] b ptbsut6 external bidirectional data bus 103 vdd pwr 104 vss gnd
s5n8947 (adsl/cable modem mcu) electronics magic team page : 14 samsung electronics 107- 118 xdata[20:31] b ptbsut6 external bidirectional data bus 119- 121 p[0: 2] b ptbst4sm general i/o ports 122 vdd_p pwr 123 vss_p gnd 124- 138 p[3:17 ] b ptbst4sm general i/o ports 139 vdd_p pwr 140 vdd_s gnd 141- 143 uto_txadr[0:2] o address bus for tx 144- 151 uto_txd[0:7] o pob4 data bus for tx 152 uto_txsoc o pob4 start of cell for tx 153 uto_txenb o pob4 enable data transfers (active low) 154 uto_txclav i ptis cell buffer available 155 vdd_p pwr vdd3op i/o pad power 156 vss_p gnd vssop i/o pad ground 157 vdd_p pwr vdd3op i/o pad power 158 vss_p gnd vssop i/o pad ground 159- 161 utop_rxadr[0:2] o address bus for rx 162- 169 uto_rxd[0:7] i ptis data bus for rx 170 uto_rxsoc i ptic start of cell for rx 171 uto_rxenb o pob4 enable data transfers (active low) 172 uto_rxclav i ptis cell buffer available 173 uto_clk o pob4 transfer/receive interface byte clock 174 vdd_i pwr 175 vss_i gnd 176 scl b ptbcd4 i 2 c serial clock 177 sda b ptbcd4 i 2 c serial data 178 uclk i ptis uart external clock for uart 179 uarxd i ptic uart receive data 180 uatxd o pob4 uart transmit data 181 nuadtr i ptic not uart0 data terminal ready 182 nuadsr o pob4 not uart0 data set ready 183 mdc o pob4 management data clock 184 mdio o ptbbcut4 management data i/o 185 col/col_10m i ptis collision detected/collision detected for 10m 186- 189 rxd[0:3]/rxd_10m i ptis receive data/receive data for 10m 190 rx_dv/link_10m i ptis receive data valid 191 vdd pwr 192 vss gnd 193 rx_clk/rxclk_10 m i ptis receive clock/receive clock for 10m 194 rx_err i ptis receive error 195 tx_clk/tx_clk_10 m i ptis transmit clock/transmit clock for 10m 196- 199 txd[0:3]/txd_10m/ loop_10m o pob4 transmit data/transmit data for 10m 200 tx_en/txen_10m o pob4 transmit enable/transmit enable for 10m 201 tx_err/pcomp_10 m o pob4 transmit error/packet compression enable for 10m 202 crs/crs_10m i ptis carrier sense/carrier sense for 10m
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 15 magic team 203 usb_dp b usb data d+ 204 usb_dn b pbusb1 usb data d- 205 tmode i ptic test mode 206 clksel i ptic clock out enable/disable 207 vdd pwr 208 vss gnd
s5n8947 (adsl/cable modem mcu) electronics magic team page : 16 samsung electronics 5. o peration d escription 5.1. cpu core overview the s5n8947 cpu core is the arm7tdmi processor, a general purpose, 32-bit microprocessor developed by advanced risc machines, ltd. (arm). the core's architecture is based on reduced instruction set computer (risc) principles. the risc architecture makes the instruction set and its related decoding mechanisms simpler and more efficient than those with microprogrammed complex instruction set computer (cisc) systems. the resulting benefit is high instruction throughput and impressive real-time interrupt response. pipelining is also employed so that all components of the processing and memory systems can operate continuously. the arm7tdmi has a 32-bit address bus. an important feature of the arm7tdmi processor, and one which differentiates it from the arm7 processor, is a unique architectural strategy called thumb. the thumb strategy is an extension of the basic arm architecture and consists of 36 instruction formats. these formats are based on the standard 32-bit arm instruction set, but have been re-coded using 16-bit wide opcodes. address register address incrementer register bank multiplier barrel shifter 32-bit alu write data register instruction decoder and logic controll instruction pipeline and read data register figure 3 arm7tdmi core block diagram because thumb instructions are one-half the bit width of normal arm instructions, they produce very high-density code. when a thumb instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in the standard arm instruction set. the arm core then processes the 16-bit instruction as it would a normal 32-bit instruction. in other words, the t humb architecture gives 16-bit systems a way to access the 32-bit performance of the arm core without incurring the full overhead of 32-bit processing. because the arm7tdmi core can execute both standard 32-bit arm instructions and 16-bit t humb instructions, it lets you mix routines of t humb instructions and arm code in the same address space. in this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application.
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 17 magic team 5.2. instruction set the s5n8947 instruction set is divided into two subsets: a standard 32-bit arm instruction set and a 16-bit thumb instruction set . the 32-bit arm instruction set is comprised of thirteen basic instruction types which can be divided into four broad classes: l four types of branch instructions which control program execution flow, instruction privilege levels, and switching between arm code and thumb code. l three types of data processing instructions which use the on-chip alu, barrel shifter, and multiplier to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths). l three types of load and store instructions which control data transfer between memory locations and the registers. one type is optimized for flexible addressing, another for rapid context switching, and the third for swapping data. l three types of co-processor instructions which are dedicated to controlling external co-processors. these instructions extend the off-chip functionality of the instruction set in an open and uniform way. note : all 32-bit arm instructions can be executed conditionally. the 16-bit thumb instruction set contains 36 instruction formats drawn from the standard 32-bit arm instruction set. the thumb instructions can be divided into four functional groups: l four branch instructions. l twelve data processing instructions, which are a subset of the standard arm data processing instructions. l eight load and store register instructions. l four load and store multiple instructions. note : each 16-bit thumb instruction has a corresponding 32-bit arm instruction with the identical processing model. the 32-bit arm instruction set and the 16-bit thumb instruction sets are good targets for compilers of many different high-level languages. when assembly code is required for critical code segments, the arm programming technique is straightforward, unlike that of some risc processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. pipelining is employed so that all parts of the processor and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. 5.3. operating states from a programmer's point of view, the arm7tdmi core is always in one of two operating states. these states, which can be switched by software or by exception processing, are: l arm state (when executing 32-bit, word-aligned, arm instructions), and l thumb state (when executing 16-bit, half-word aligned thumb instructions).
s5n8947 (adsl/cable modem mcu) electronics magic team page : 18 samsung electronics 5.4. operating modes the arm7tdmi core supports seven operating modes: l user mode: the normal program execution state l fiq (fast interrupt request) mode: for supporting a specific data transfer or channel process l irq (interrupt request) mode: for general purpose interrupt handling l supervisor mode: a protected mode for the operating system l abort mode: entered when a data or instruction pre-fetch is aborted l system mode: a privileged user mode for the operating system l undefined mode: entered when an undefined instruction is executed operating mode changes can be controlled by software, or they can be caused by external interrupts or exception processing. most application programs execute in user mode. privileged modes (that is, all modes other than user mode) are entered to service interrupts or exceptions, or to access protected resources. 5.5. registers the s5n8947 cpu core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers. not all of these registers are always available. which registers are available to the programmer at any given time depends on the current processor operating state and mode. note : when the s5n8947 is operating in arm state, 16 general registers and one or two status registers can be accessed at any time. in privileged mode, mode-specific banked registers are switched in. two register sets, or banks, can also be accessed, depending on the core's current state: the arm state register set and the thumb state register set: l the arm state register set contains 16 directly accessible registers: r0-r15. all of these registers, except for r15, are for general-purpose use, and can hold either data or address values. an additional (seventeenth) register, the cpsr (current program status register), is used to store status information. l the thumb state register set is a subset of the arm state set. you can access eight general registers, r0-r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. each privileged mode has a corresponding banked stack pointer, link register, and saved process status register (spsr). the thumb state registers are related to the arm state registers as follows: l thumb state r0-r7 registers and arm state r0-r7 registers are identical l thumb state cpsr and spsrs and arm state cpsr and spsrs are identical l thumb state sp, lr, and pc map directly to arm state registers r13, r14, and r15, respectively in thumb state, registers r8-r15 are not part of the standard register set. however, you can access them for assembly language programming and use them for fast temporary storage, if necessary. 5.6. exceptions
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 19 magic team an exception arises whenever the normal flow of program execution is interrupted. for example, when processing must be diverted to handle an interrupt from a peripheral. the processor's state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. multiple exceptions may arise simultaneously. to process exceptions, the s5n8947 uses the banked core registers to save the current state. the old pc value and the cpsr contents are copied into the appropriate r14 (lr) and spsr register. the pc and mode bits in the cpsr are forced to a value which corresponds to the type of exception being processed. the s5n8947 core supports seven types of exceptions. each exception has a fixed priority and a corresponding privileged processor mode, as shown in following table exception mode on entry priority reset supervisor mode 1 (highest) data abort abort mode 2 fiq fiq mode 3 irq irq mode 4 prefetch abort abort mode 5 undefined instruction undefined mode 6 swi supervisor mode 6 (lowest) table 2 s5n8947 cpu exceptions
s5n8947 (adsl/cable modem mcu) electronics magic team page : 20 samsung electronics 6. h ardware s tructure 6.1. system manager 6.1.3. overview the s5n8947 microcontroller ? s system manager has the following functions. l to arbitrate system bus access requests from several master blocks, based on fixed priorities. l to provide the required memory control signals for external memory accesses. for example, if a master block such as the dma controller or the cpu generates an address which corresponds to a dram bank, the system manager ? s dram controller generates the required normal/edo or sdram access signals. the interface signals for normal/edo or sdram can be switched by syscfg[31]. l to provide the required signals for bus traffic between the s5n8947 and rom/sram and the external i/o banks. l to compensate for differences in bus width for data flowing between the external memory bus and the internal data bus. l to support both little and big endian for external memory or i/o devices. internal registers, however, operate under big-endian mode. note : by generating an external bus request (extmreq), an external device can access the s5n8947 ? s external memory. the s5n8947 can access slow external devices using a ndtack signal. the dtack signal, which is generated by the external device, extends the duration of the cpu ? s memory access cycle beyond its programmable value. 6.1.4. system manager registers to control external memory operations, the system manager uses a dedicated set of special registers. by programming the values in the system manager special registers, you can specify such things as : l memory type l external bus width access cycle l control signal timing (ras and cas, for example) l memory bank locations l size of each memory bank to be used for arbitrary address spacing the system manager uses special register setting to control the generation and processing of the control signals, addresses, and data that are required by external devices in a standard system configuration. special registers are also used to control access to rom/sram/flash banks, up to four dram banks and four external i/o banks, and a special register mapping area.
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 21 magic team the address resolution for each memory bank base pointer is 64 kbytes (16 bits). the base address pointer is 10 bits. this gives a total addressable memory bank space of 16 m words. rom/sram/flash bank 0 rom/sram/flash bank 1 rom/sram/flash bank 2 rom/sram/flash bank 3 dram/sdram bank 0 dram/sdram bank 1 dram/sdram bank 2 dram/sdram bank 3 external i/o bank 0 external i/o bank 1 external i/o bank 2 external i/o bank 3 internal sram special register bank reserved 16 m words (16 m x 32 bits) sa[25:0] 16 k words (fixed) 4 k words (fixed for all i/o banks) continuous 16 k word space for 4 external i/o banks 4 k bytes (fixed) 16 k words - 4 m words (32 bits) addr[21:0] 0x3ffffff 0x0000000 figure 4 s5n8947 system memory map 6.1.5. system memory map followings are several important features to note about the s5n8947 system memory map : l the size and location of each memory bank is determined by the register settings for ? current bank base pointer ? and ? current bank end pointer ? . you can use this base/next bank pointer concept to set up a consecutive memory map. to do this, you set the base pointer of the ? next bank ? to the same address as the next pointer of the ? current bank ? . please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. this can be applied even if one or more banks are disabled.
s5n8947 (adsl/cable modem mcu) electronics magic team page : 22 samsung electronics l four external i/o banks are defined in a continuous address space. a programmer can only set the base pointer for external i/o bank 0. the start address of external i/o bank 1 is then calculated as the external i/o bank 0 start address +16 k. similary, the start address for external i/o bank 2 is the external i/o bank 0 start address + 32 k, and the start address for external i/o bank 3 is the external i/o bank 0 start address + 48 k. therefore, the total consecutive addressable space of the four external banks is defined as the start address of external i/o bank 0 + 64 k bytes. l within the addressable space, the start address of each i/o bank is not fixed. you can use bank control registers to assign a specific bank start address by setting the bank ? s base pointer. the address resolution is 64 k bytes. the bank ? s start address is defined as ? base pointer << 16 ? and the bank ? s end address (except for external i/o banks) is ? next pointer << 16 ? 1 ? . after a power-on or system reset, all bank address pointer registers are initialized to their default values. in this means that a system reset automatically defines rom bank 0 as a 32-mbyte space with a start address of zero. this means that, except for rom bank 0, all banks are undefined following a system startup. the reset value for the next pointer and base pointer of rom bank 0 are 0x200 and 0x000, respectively. this means that a system reset automatically defines rom bank 0 as a 32-mbyte space with a start address of zero. this initial definition of rom bank 0 lets the system power-on or reset operation pass control to the user-supplied boot code that is stored in external rom. (this code is located at address 0 in the system memory map.) when the boot code (i.e. rom program) executes, it performs various system initialization tasks and reconfigures the system memory map according to the application ? s actual external memory and device configuration. the initial system memory map following system startup is shown in following : rom/sram/flash bank 0 area (accessible) undefined area special function registers 4 m address[21:0] rom/sram/flash bank 0 area (accessible) 32 m 64 m bytes sa[25:0] 0x0000000 0x2000000 0x3ff0000 0x3ffffff figure 5 initial system memory map (after reset)
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 23 magic team 6.2. instruction / data cache the s5n8947 cpu has a unified internal 4-kbyte instruction/data cache. the cache is configured using two-way, set-associative addressing. the replacement algorithm is pseudo-lru (least recently used). the cache line size is four words (16 bytes). when a miss occurs, four word must be fetched consecutively from external memory. typically, risc processors take advantage of unified instruction/data caches to improve performance. switch cs set 1 tag set 0 tag 15 2 tag ram (32-bit) set 1 icache line = 4 instruction/data (128-bit) set 0 icache line = 4 instruction/data (128-bit) decoder 6-bit 2-bit height = 128 7-bit height = 128 32 2 (set 0 hit) (set 1 hit) 15 enable non-cacheable control 100: set 0 direct access 101: set 1 direct access 110: tag direct access 15 2 32 32 instr3 instr2 instr1 instr0 32-bit instr3 instr2 instr1 instr0 32-bit 7-bit 31 27 28 tag address (15-bit) 25 0 30 29 26 10 9 4 3 2 1
s5n8947 (adsl/cable modem mcu) electronics magic team page : 24 samsung electronics 6.3. i 2 c bus controller the s5n8947 ? s internal ic bus (i 2 c-bus) controller has the following important features : l it requires only two bus lines, a serial data line (sda) and a serial clock line (scl). when the i 2 c-bus is free, both lines are high level. l each device that is connected to the bus is software-addressable by a unique address. slave relationships on the bus are constant. the bus master can be either a master-transmitter or a master- receiver. the i 2 c bus controller supports only single master mode. l it supports 8-bit, bi-directional, serial data transfers. l the number of ics that you can connect to the same i 2 c-bus is limited only by the maximum bus capacitance of 400 pf. following figure shows a block diagram of the s5n8947 ? s i 2 c-bus controller. data control scl control serial clock prescaler control status register (iiccon) 0 busy cond1 cond0 ack lrb ien prescaler register (iicps) system clock (fmclk) 16 scl sda bf shift buffer register (iicbuf) figure 6 i 2 c-bus block diagram
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 25 magic team 6.4. ethernet controller the s5n8947 has an ethernet controller which operates at either 100/ 10-mbits per second in half- duplex or full-duplex mode. in half-duplex mode, the controller supports the ieee 802.3 carrier sense multiple access with collision detection (csma/cd) protocol. in full-duplex mode, it supports the ieee 802.3 mac control layer, including the pause operation for flow control. 6.4.1. block diagram s y s t e m b u s b d i m i i / 10 m b p s 7 - w i r e bdma tx buffer controller bdma tx buffer (64 words) bus arbiter/ controller bdma rx buffer (64 words) bdma rx buffer controller cam contents memory (32-words) bdma control and status register max tx buffer (80 bytes) max tx buffer controller mac max rx buffer (16 bytes) max rx buffer controller address cam interface and comparator flow controller crc checker mac control and status register station manager bdma+sbus i/f 32 32 32 32 32 32 8 8 figure 7 ethernet controller block diagram 6.4.2. features and benefits the most important features and benefits of the s5n8947 ethernet controller are follows : l cost-effective connection to an external repeater interface controller( ric ) /ethernet backbone l buffered dma (bdma) engine using burst mode l bdma tx/rx buffers (256 bytes/256 bytes) l mac tx/rx fifos (80 bytes/16 bytes) to support re-transmit after collision without dma request and to handle dma latency l data alignment logic l support s for old and new media (compatible with existing 10-mbit/s networks) l full ieee 802.3 compatibility for existing applications l provides a standard media independent interface (mii) l provides an external 7-wire interface , also.
s5n8947 (adsl/cable modem mcu) electronics magic team page : 26 samsung electronics l station management (sta) signaling for external physical layer configuration and link negotiation l on-chip cam (21 addresses) l full-duplex mode for doubled bandwidth l pause operation hardware support for full-duplex flow control l long packet mode for specialized environments l short packet mode for fast testing l pad generation for ease of processing and reduced processing time l support for old and new media : compatible with existing 100/ 10mbit/s networks. l full ieee 802.3 compatibility : compatible with existing hardware and software. l standard csma/cd,full duplex capability at 100/ 10 mbit/s : increase in data throughput performance.
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 27 magic team 6.5. sar and utopia interface the s5n8947 provides atm layer segmentation and reassembly (sar) function over a 8bit utopia interface. the s5n8947 delivers an integrated solution for performing the sar tasks required to communicate over an atm network. the device translates packet-based data into 53-byte atm cells that are asynchronously mapped into various physical media. the s5n8947 can be effectively applied for equipment requiring an interface between packet-based data and atm-based networks. 6.5.1. block diagram reassembler aal5, 3/ 4, 0 segmentor aal5, 3/4, 0 scheduler (cbr,ubr,rt-vbr,nrt-vbr) registers connection memory (internal and/or external) utopia and fifos system i/f and fifos figure 8 sar function block diagram 6.5.2. features and benefits l supports cbr, ubr, rt-vbr and nrt-vbr traffic with rates set on a per-vc or per-vp basis. l supports aal0 (raw cells) and aal5 segmentation and reassembly. l segments and reassembles data up to about 70m bps via utopia interface. l generates and verifies crc-10 for oam cells and aal3/4 cells. l supports concurrent oam cells and aal5 cells on each active connection. l supports simultaneous segmentation and reassembly of up to 32 connections with internal memory and up to 4k connections with external memory. l on chip 8k bytes sram for internal connection memory. l supports contents addressable memory (cam) for channel mapping (up to 32 connections). l supports packet sizes up to 64k bytes. l supports scatter and gather packet capability for large packets l start of packet offset available for ease of implementing bridging and routing between different protocols. l provides glue-less utopia level 2 interface (up to 7 phys).
s5n8947 (adsl/cable modem mcu) electronics magic team page : 28 samsung electronics 6.6. usb controller the universal serial bus (usb) is an industry standard bus architecture for computer peripheral attachment. the usb provides a single interface for easy, plug-and-play, hot-plug attachment of peripherals such as keyboard, mouse, speakers, printers, scanners, and communication devices. the usb allows simultaneous use of many different peripherals with a combined transfer rate of up to 12 mbit/s. the s5n849 7 controller includes a highly flexible integrated usb peripheral controller that lets designers implement a variety of microcontroller-based usb peripheral devices for telephony, audio, or other high-end applications. the s5n8947 controller is intended for usb peripherals that use the full- speed signalling rate of 12 mbit/s. the usb low-speed rate (1.5 mbit/s) is not supported. an integrated usb transceiver is provided to minimize system device count and cost, but an external transceiver can be used instead, if required. the usb peripheral controller ? s features meet or exceed all of the usb device class resource requirements defined by the usb specification version 1.0 and 1.1. consult the usb specification for details about overall usb system design. the integrated usb peripheral controller provides a very efficient and easy-to-use interface, so that device software (or firmware) does not incur the overhead of managing low-level usb protocol requirements. the usb peripheral controller hardware implements a number of usb standard commands directly; the rest can be implemented in device software. in addition, the usb peripheral controller provides a high degree of flexibility to help designers accommodate vendor- or device-class-specific commands, as well as any new features that might be added in future usb specifications. specialized hardware is provided to support bulk data transfers. using the microcontroller ? s dma features, large size of bulk transfers from an off-chip peripheral, can be automatically synchronized to the usb data rate with little or no cpu overhead. robust error detection and management features are provided so the device software can manage transfers in any number of ways as required by the application. the usb suspend/ resume, reset, and remote wake up features are also supported. 6.6.1. block diagram serial interface engine (sie) serial interface unit (sie) endpoint 1 16 out fifo endpoint 0 fifo endpoint 2 16 in fifo mcu address decoder host mcu / dma interface endpoint 3 64 out fifo endpoint 4 64 in fifo x 2 x 2 figure 9 usb module block diagram
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 29 magic team 6.7. dma controller the s5n8947 has a two-channel general dma controller, called the gdma. the two-channel gdma performs the following data transfers without cpu intervention: l memory-to-memory (memory to/from memory) l uart-to-memory (serial port to/from memory) l usb-to-memory (usb port to/from memory) the on-chip gdma can be started by software and/or by an external dma request (nxdreq). software can also be used to restart a gdma operation after it has been stopped. the cpu can recognize when a gdma operation has been completed by software polling and/or when it receives an appropriate internally generated gdma interrupt. the s5n8947 gdma controller can increment or decrement source or destination addresses and conduct 8-bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. system bus gdma channel 0 ndreq ndack gdma channel 1 ndreq ndack port 14 data gdma0 iopcon [27:26] nxdack 0 iopcon [29:28] nxdack 1 port 15 data gdma1 mode selection mode selection nxdreq 1 usb (to memory) uart nxdreq 0 usb (from memory) figure 10 gdma controller block diagram
s5n8947 (adsl/cable modem mcu) electronics magic team page : 30 samsung electronics 6.8. uart(serial i/o) the s5n8947 uart (universal asynchronous receiver/transmitter) unit provides an asynchronous serial i/o (sio) port. this can operate in interrupt-based or dma-based mode. that is, the uart can generate internal interrupts or dma requests to transfer data between the cpu and the serial i/o port. the most important features of the s5n8947 uart include: l programmable baud rates l infra-red (ir) transmit/receive l insertion of one or two stop bits per frame l selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers l parity checking this unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in next figure . the baud-rate generator can be driven by the internal system clock, mclk. the transmitter and receiver block use this baud rate clock and have independent data buffer registers and data shifters. transmit data is written first to the transmit buffer register. from there, it is copied to the transmit shifter and then shifted out by the transmit data pin, uatxdn. receive data is shifted in by the receive data pin, uarxdn. it is then copied from the shifter to the receive buffer register when one data byte has been received. this unit provide s software controls for mode selection, and for status and interrupt generation. transmit buffer register (utxbufn) transmit shift register baud rate generator baud rate divisor (utbufn) system bus receive buffer register (urxbufn) receive shift register line control register (ulconn) uart status register (ustatn) uart control register (uconn) ir rx decoder uarxdn nuadtrn nuadsrn ir rx decoder 0 1 0 1 uatxdn figure 11 uart block diagram
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 31 magic team 6.9. timers the s5n8947 has two 32-bit timers. these timers can operate in interval mode or in toggle mode. the output signals are tout0 and tout1, respectively. you enable or disable the timers by setting control bits in the timer mode register, t mod . an interrupt request is generated whenever a timer count-out (down count) occurs. watchdog timer is also implemented in the s5n8947. the following guidelines apply to watchdog timer functions : ? when a watchdog timer is enabled, it loads a data value to its count register and begins decrementing the count register value by the system clock . ? if the reset from the w atchdog timer (wdreset) reaches to zero , the watchdog will start its reset s equence . the reset value is then reloaded and the watchdog timer is disabled . ? the wdreset performs the same function as the external reset (system reset) to each block . f mclk 32-bit timer count register (tcntn) [down counter] 32-bit timer data register (tdatan) pulse generator tmod.ten tmod.tmdn tmod.tclrn pnd intpnd and intmsk interrupt request port 16, port 17 data out iopcon.toenn auto re-load toutn figure 12 32-bit timer block diagram
s5n8947 (adsl/cable modem mcu) electronics magic team page : 32 samsung electronics 6.10. i/o ports the s5n8947 has 18 programmable i/o ports. you can configure each i/o port to input mode, output mode, or special function mode. to do this, you write the appropriate settings to the iopmod and iopcon registers. user can set filtering for the input ports using iopcon register. the modes of the ports from port0 to port7 are determined only by the iopmod register. but port[11:8] can be used as xintreq[3:0], port[13:12] as nxdreq[1:0], port[15:14] as nxdack[1:0], port[16] as tout0, or port[17] as tout1 depending on the settings in iopcon register. system bus output latch input latch active on/off & edge detection iopdata (read) interrupt or dma request iopcon filter on/off iopcon iopdata (write) alternate functions iopcon v dd iopmod port0 - port7 port8/xintreq0 port11/xintreq3 port12/nxdreq0 port13/nxdreq1 port14/nxdack0 port15/nxdack1 port16/tout0 port17/tout1 figure 13 i/o port function diagram
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 33 magic team 6.11. interrupt controller the s5n8947 interrupt controller has a total of 18 interrupt sources. interrupt requests can be generated by internal function blocks and external pins. the arm7tdmi core recongnizes two kinds of interrupts: a normal interrupt request (irq), and a fast interrupt request (fiq). therefore all s5n8947 interrupts can be categorized as either irq or fiq. the s5n8947 interrupt controller has an interrupt pending bit for each interrupt source. four special registers are used to control interrupt generation and handling: l interrupt priority registers. the index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority. the interrupt priorities are pre-defined from 0 to 17 . l interrupt mode register. defines the interrupt mode, irq or fiq, for each interrupt source. l interrupt pending register. indicates that an interrupt request is pending. if the pending bit is set, the interrupt pending status is maintained until the cpu clears it by writing a "1" to the appropriate pending register. when the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". the service routine must clear the pending condition by writing a "1" to the appropriate pending bit. this avoids the possibility of continuous interrupt requests from the same interrupt pending bit. l interrupt mask register. indicates that the current interrupt has been disabled if the corresponding mask bit is "1". if an interrupt mask bit is "0" the interrupt will be serviced normally. if the global mask bit (bit 18 ) is set to "1", no interrupts are serviced. however, the source's pending bit is set if the interrupt is generated. when the global mask bit has been set to "0", the interrupt is serviced. index values interrupt sources [17] i 2 c-bus interrupt [16] ethernet controller mac rx interrupt [15] ethernet controller mac tx interrupt [14] ethernet controller bdma rx interrupt [1 3 ] ethernet controller bdma tx interrupt [12] sar tx/rx done interrupt [11] sar tx/rx error interrupt [10] usb interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] timer 1 interrupt [6] timer 0 interrupt [5] uart receive and error interrupt [4] uart transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 table 3 s5n8947 interrupt sources
s5n8947 (adsl/cable modem mcu) electronics magic team page : 34 samsung electronics 7. special function registers group registers offset r/w description reset/value syscfg 0x0000 r/w system configuration register 0x 23ff0000 syscon 0x3000 r/w system control register 0x00000000 extacon0 0x3008 r/w external i/o timing register 1 0x00000000 extacon1 0x300c r/w external i/o timing register 2 0x00000000 extdbwth 0x3010 r/w data bus width for each memory bank 0x00000000 romcon0 0x3014 r/w rom/sram/flash bank 0 control register 0x20000060 romcon1 0x3018 r/w rom/sram/flash bank 1 control register 0x00000060 romcon2 0x301c r/w rom/sram/flash bank 2 control register 0x00000060 romcon3 0x3020 r/w rom/sram/flash bank 3 control register 0x00000060 dramcon0 0x3024 r/w dram bank 0 control register 0x00000000 dramcon1 0x3028 r/w dram bank 1 control register 0x00000000 dramcon2 0x302c r/w dram bank 2 control register 0x00000000 dramcon3 0x3030 r/w dram bank 3 control register 0x00000000 system manager refextcon 0x3034 r/w refresh and external i/o control register 0x83fd0000 bdmatxcon 0x9000 r/w buffered dma receive control register 0x00000000 bdmarxcon 0x9004 r/w buffered dma transmit control register 0x00000000 bdmatxptr 0x9008 r/w transmit trame descriptor start address 0x00000000 bdmarxptr 0x900c r/w receive frame descriptor start address 0x00000000 bdmarxlsz 0x9010 r/w receive frame maximum size undefined bdmastat 0x9014 r/w buffered dma status 0x00000000 cam 0x9100- 0x917c r/ w cam content (32 words) undefined bdmatxbuf 0x9200- 0x92fc r/w bdma tx buffer (64 words) for test mode addressing undefined ethernet (bdma) bdmarxbuf 0x9800- 0x99fc r/w bdma rx buffer (64 words) for test mode addressing undefined macon 0xa000 r/w ethernet mac control register 0x00000000 camcon 0xa004 r/w cam control register 0x00000000 mactxcon 0xa008 r/w mac transmit control register 0x00000000 mactxstat 0xa00c r/w mac transmit status register 0x00000000 macrxcon 0xa010 r/w mac receive control register 0x00000000 macrxstat 0xa014 r/w mac receive status register 0x00000000 stadata 0xa018 r/w station management data 0x00000000 stacon 0xa01c r/w station management control and address 0x00006000 camen 0xa028 r/w cam enable register 0x00000000 emisscnt 0xa03c r/w missed error count register 0x00000000 epzcnt 0xa040 r pause count register 0x00000000 ermpzcnt 0xa044 r remote pause count register 0x00000000 ethernet (mac) etxstat 0x9040 r transmit control frame status 0x00000000 fa 0x7000 r/w function address register 0x 0 000000 0 pm 0x7004 r/w power management register 0x 000000 00 ei 0x7008 r/w endpoint interrupt register 0x 000000 00 ui 0x700c r/w usb interrupt register 0x 000000 00 eie 0x7010 r/w endpoint interrupt enable register 0x0000001f uie 0x7014 r/w usb interrupt enable register 0x00000004 usb lbfn 0x7018 r frame number1 register 0x 000000 0 0
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 35 magic team hbfn 0x701c r frame number2 register 0x 000000 00 ie0m 0x7020 r/w input ep0 maxp register 0x 000000 00 *e0c 0x7024 r/w ep0 control register 0x 000000 00 *e0bc 0x7028 r/w ep0 write byte counter 0x00000000 *o1m 0x7030 r/w ep1 out maxp register 0x 000000 01 *o1c1 0x7034 r/w ep1 out control register 1 0x 000000 00 *o1c2 0x7038 r/w ep1 out control register 2 0x 000000 00 *e1bc 0x703c r/w ep1 write byte counter 0x00000000 *i2m 0x7040 r/w ep2 in maxp register 0x00000001 *i2c1 0x7044 r/w ep2 in control register 1 0x 000000 0 0 *i2c2 0x7048 r/w ep2 in control register 2 0x 000000 00 *o3m 0x7050 r/w ep 3 out maxp register 0x 00000004 *o3c1 0x7054 r/w ep 3 out control register 1 0x 000000 00 *o3c2 0x7058 r/w ep3 out control register 2 0x 000000 00 *e3bc 0x705c r/w ep3 write byte counter 0x00000000 *i4m 0x7060 r/w ep4 in maxp register 0x00000004 *i4c1 0x7064 r/w ep4 in control register 1 0x 000000 0 0 *i4c2 0x706c r/w ep4 in control register 2 0x 000000 00 *pdc 0x7070 r/w power-down counter register 0x00000000 *ep0d 0x7100 r/w ep0 fifo data register 0x00000000 *ep1d 0x7104 r/w ep1 fifo data register 0x00000000 *ep2d 0x7108 r/w ep2 fifo data register 0x00000000 *ep3d 0x710c r/w ep3 fifo data register 0x00000000 *ep4d 0x7110 r/w ep4 fifo data register 0x00000000 sw_reset 0x00 r/w software reset register 0x00000000 global_mode 0x08 r/w global mode register 0x00000000 timeout_base 0x0c r/w base multiple for receive packet timeout register 0x00ff7fff tx_ready1 0x10 r/w transmit ready first packet or subpacket address 0x00000000 tx_ready2 0x14 r/w transmit ready last packet or subpacket address 0x00000000 tx_done_addr 0x18 r/w transmit packet done queue base address register 0x00000000 tx_done_size 0x1c r/w transmit packet done queue size register 0x00c00000 rx_pool0_addr 0x20 r/w receive queue 0 base address register 0x00000000 rx_pool0_size 0x24 r/w receive queue 0 size register 0x00c00000 rx_pool1_addr 0x28 r/w receive queue 1 base address register 0x00000000 rx_pool1_size 0x2c r/w receive queue 1 size register 0x00c00000 rx_pool2_addr 0x30 r/w receive queue 2 base address register 0x00000000 rx_pool2_size 0x34 r/w receive queue 2 size register 0x00c00000 rx_pool3_addr 0x38 r/w receive queue 3 base address register 0x00000000 rx_pool3_size 0x3c r/w receive queue 3 size register 0x00c00000 rx_done0_addr 0x40 r/w receive packet done queue 0 base address register 0x00000000 rx_done0_size 0x44 r/w receive packet done queue 0 size register 0x00c00000 rx_done1_addr 0x48 r/w receive packet done queue 1 base address register 0x00000000 rx_done1_size 0x4c r/w receive packet done queue 1 size register 0x00c00000 utopia_config 0x50 r/w utopia interface configuration register 0x00000000 utopia_timeout 0x54 r/w utopia interface timeout register 0xffffffff clock_ratio 0x64 r/w ratio of sar clock freq touni interface speed 0x0000008e done_int_mask 0x70 r/w interrupt mask for done interrupt register 0xffffffff err_int_mask 0x74 r/w interrupt mask for error interrupt register 0xffffffff done_int_stat 0x78 r/w interrupt status for done interrupt register 0x00000000 err_int_stat 0x7c r/w interrupt status for error interrupt register 0x00000000 1/r_lookup_tbl 0x80 r/w base address of 1/rate lookup table 0x00000000 vp_lookup_tbl 0x84 r/w base address of vp lookup table 0x00000200 ubr_sch_tbl 0x88 r/w base address and entry number of ubr schedule 0x00000300 sar cbr_sch_tbl 0x8c r/w base address and entry number of cbr schedule 0x00000380
s5n8947 (adsl/cable modem mcu) electronics magic team page : 36 samsung electronics cell_buff 0x90 r/w base address and entry number of cell buffer 0x00000400 sch_conn_tbl 0x94 r/w base address and entry number of scheduler connection table 0x00000500 aal_conn_tbl 0x98 r/w base address and entry number of aal connection table 0x00000600 sar_conn_tbl 0x9c r/w base address and entry number of sar connection table 0x00000700 cam_vpvc/cn 0x100-1fc r/w cam vpci, vci and connection number register 0x00000000 configuration 0x200 r/w clock control and connection memory configuration register 0x000000 44 ext_cmbase 0x204 r/w external connection memory base address register 0x00000 0 00 iopmod 0x5000 r/w i/o port mode register 0x00000000 iopcon 0x5004 r/w i/o port control register 0x00000000 i/o ports iopdata 0x5008 r/w input port data register undefined intmod 0x4000 r/w interrupt mode register 0x00000000 intpnd 0x4004 r/w interrupt pending register 0x00000000 intmsk 0x4008 r/w interrupt mask register 0x003fffff intpri0 0x400c r/w interrupt priority register 0 0x0 3020100 intpri1 0x4010 r/w interrupt priority register 1 0x07060504 intpri2 0x4014 r/w interrupt priority register 2 0x0b0a0908 intpri3 0x4018 r/w interrupt priority register 3 0x0f0e0d0c intpri4 0x401c r/w interrupt priority register 4 0x 0000 1110 intpri5 0x4020 r/w interrupt priority register 5 0x000000 00 intoffset 0x4024 r interrupt offset address register 0x000000 54 int pndpri 0x4028 r interrupt pending priority register 0x000000 00 int pndtst 0x402 c w interrupt pending test register 0x000000 00 intoset_fiq 0x4030 r fiq interrupt offset register 0x00000054 interrupt controller intoset_irq 0x4034 r irq interrupt offset register 0x00000054 iiccon 0xf000 r/w i 2 c bus control status register 0x000000 00 iicbuf 0xf004 r/w i 2 c bus shift buffer register undefined iicps 0xf008 r/w i 2 c bus prescaler register 0x00000000 i 2 c bus iiccount 0xf00c r i 2 c bus prescaler counter register 0x00000000 gdmacon0 0xb000 r/w gdma channel 0 control register 0x00000000 gdmacon1 0xc000 r/w gdma channel 1 control register 0x00000000 gdmasrc0 0xb004 r/w gdma source address register 0 undefined gdmadst0 0xb008 r/w gdma destination address register 0 undefined gdmasrc1 0xc004 r/w gdma source address register 1 undefined gdmadst1 0xc008 r/w gdma destination address register 1 undefined gdmacnt0 0xb00c r/w gdma channel 0 transfer count register undefined gdma gdmacnt1 0xc00c r/w gdma channel 1 transfer count register undefined ulcon 0xd000 r/w uart line control register 0x xxxxxx 00 ucon 0xd004 r/w uart control register 0x xxxxxx 00 ustat 0xd008 r uart status register 0x xxxxxx c0 utxbuf 0xd00c w uart transmit holding register undefined urxbuf 0xd010 r uart receive buffer register undefined uart ubrdiv 0xd014 r/w baud rate divisor register 0xxxxxxx00 tmod 0x6000 r/w timer mode register 0x00000000 tdata0 0x6004 r/w timer 0 data register 0x00000000 tdata1 0x6008 r/w timer 1 data register 0x00000000 tcnt0 0x600c r/w timer 0 count register 0x ffffffff tcnt1 0x6010 r/w timer 1 count register 0x ffffffff wdcon 0x6014 r/w watchdog timer control register 0x ffffff00 timers wdcnt 0x6018 r watchdog timer count register 0x ffffffff
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 37 magic team 8. electric characteristics 8.1. absolute maximum ratings parameter symbol rating units supply voltage v dd /v dda 3.6 v dc input voltage v in 2.5 v i/o 3.6 v 5 v-tolerant 6.5 dc input current i in 200 ma operating temperature t opr 0 to 70 o c storage temperature t stg ? 65 to 150 o c table 4 absolute maximum ratings 8.2. r ecommended operating conditions parameter symbol rating units supply voltage v dd /v dda 2.3 to 2.7 v oscillator frequency f osc 12 mhz external loop filter capacitance l f 820 pf commercial temperature t a 0 to 70 o c table 5 recommaended operating conditions notes it is strongly recommended that all the su pply pins (vdd/vdda) be powered from the same source to avoid power latch-up.
s5n8947 (adsl/cable modem mcu) electronics magic team page : 38 samsung electronics 8.3. dc electrical characteristics v dd = 2.5 v+/-0. 2 v, vext = 5+/-0.25v, ta= -4 0 to 85 centigrade (in case of 5v-tolerant i/o) parameter symbol conditions min typ max unit high level input voltage lvcmos interface v ih (1) ? 1.7 ? ? v low level input voltage lvcmos interface v il (1) ? ? ? 0. 7 v switching threshold vt lvcmos ? 0.5 v dd ? v schmitt trigger positive-going threshold vt+ lvcmos ? ? 1.9 ? schmitt trigger negative-going threshold vt ? lvcmos 0. 6 ? ? ? high level input current input buffer i ih v in = v dd ? 10 ? 10 a input buffer with pull-up 10 25 5 0 low level input current input buffer i lh v in = v ss ? 10 ? 10 a input buffer with pull-up ? 5 0 ? 25 ? 10 high level output voltage type b1 to b16 (2) v oh i oh = ? a v dd ? 0.05 ? ? v type b1 i oh = ? 1 ma 1.9 type b2 i oh = ? 2 ma type b4 i oh = ? 4 ma type b6 i oh = ? 6 ma low level output voltage type b1 to b16 (2) v ol i ol = ? a 0.05 v type b1 i ol = ? 1 ma 0. 5 type b2 i ol = ? 2 ma type b4 i ol = ? 4 ma type b6 i ol = ? 6 ma tri-state output leakage current i oz v out = v ss or v dd ? 10 10 a maximum operating current i dd v dd = 3.6 v , f mclk = 50mhz 55 m a table 6 dc electrical characteristics notes: 1. all 5v-tolerant input have less than 0.2v hysterisis. 2. type b1 means 1ma output driver cells, and type b6/b24 means 6ma/24ma output driver cells.
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 39 magic team 8.4. a.c electrical characteristics (ta = -4 0 to + 85 centigrade, v dd = 2.3 v to 2.7 v) signal name description min max unit t emz memory control signal high-z time 5.1 10.1 ns t emrs extmreq setup time 0 t emrh extmreq hold time 3.0 t emar extmack rising edge delay time 12.1 29.3 t emaf extmack falling edge delay time 12.3 29.7 t addrh address hold time 8.5 t addrd address delay time 7.08 17.5 t nrcs rom/sram/flash bank chip select delay time 5.2 12.4 t nroe rom/sram or external i/o bank output enable delay 5.7 13.6 t nwbe rom/sram or external i/o bank write byte enable delay 5.5 13.1 t rdh read data hold time 3.0 t wdd write data delay time (sram or external i/o) 17.23 t wdh write data hold time (sram or external i/o) 9.4 t nrasf dram row address strobe active delay 5.6 13.4 t nrasr dram row address strobe release delay 4.3 16.38 t ncasf dram column address strobe active delay 5.5 13.1 t ncasr dram cas signal release delay time 4.36 13.1 t ndwe dram bank write enable delay time 5.8 13.9 t ndoe dram bank out enable delay time 5.7 13.6 t necs external i/o bank chip select delay time 5.3 12.5 t wddd dram write data delay time (dram) 5.9 14.2 t wddh dram write data hold time (dram) 7.4 t ws external wait setup time 0 t wh external wait hold time 3.0 t mclkod external clock to mclko delay time when pll power-down 5.0 12.45 table 7 ac electrical characteristics
s5n8947 (adsl/cable modem mcu) electronics magic team page : 40 samsung electronics t em z address, data, noe, nwbe, ndwe, nrcs, ncas, nras extmreq extmack t emr s t emr h t emr f t emar xclk figure 14 external bus request timing
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 41 magic team tws newait data(r) nwbe noe tcos necs tacs tcoh address xclk tnecs taddrd tnroe tacc tnroe tnecs taddrh trdh twh tcoh = 0 tcoh = 1 data fetch (tcoh = 0) data fetch (tcoh = 1) figure 15 external i/o read timing with newait (t coh = 1, t acc = 1, t cos = 1, t acs = 1)
s5n8947 (adsl/cable modem mcu) electronics magic team page : 42 samsung electronics nwbe necs tacs tcoh address xclk tnecs taddrd tnroe tnroe tnecs taddrh tws newait data(w) trdh twh tcoh = 0 tcoh = 1 data fetch (tcoh = 0) data fetch (tcoh = 1) figure 16 external i/o write timing with newait (t coh = 1, t acc = 1, t cos = 1, t acs = 1)
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 43 magic team noe nrcs address xclk taddrh data(r) tnrcs tnroe tacc taddrd tnrcs trdh tnroe figure 17 rom/sram/flash read access timing nwbe nrcs address xclk data(w) taddrh tnrcs tnrwe twdd tacc taddrd tnrcs tnrwe twdh figure 18 rom/sram/flash write access timing
s5n8947 (adsl/cable modem mcu) electronics magic team page : 44 samsung electronics address ncas xclk trc tncasr tncasw tncasf tncasf tncasr tcs tcs tcp taddrd row address column address column address data(r) twddh trp nras tnrasf tnrasr noe tndwe edo taddrh fetch time (edo dram) fetch time (edo dram) tndoe figure 19 edo/fp dram bank read timing (page mode)
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 45 magic team address ncas xclk trc tncas r tncasw tncasf tncas f tncas r tcs tcs tcp taddrd row address column address column address data(w) twddh trp nras tnrasf tnrasr ndwe tndwe taddr h tndwe twddd twddh twddd figure 20 edo/fp dram bank write timing (page mode) timing parameters for mii transactions the timing diagrams in this section conform to the guidelines described in the "draft supplement to ansi/ieee std. 802.3, section 22.3, signal characteristics." 0ns min, 25ns max tx_clk txd[3:0] tx_en figure 21 transmit signal timing relationship at mii rx_clk rxd[3:0], rx_dv, rx_er input valid 10ns min 10ns min figure 22 receive signal timing relationship at mii
s5n8947 (adsl/cable modem mcu) electronics magic team page : 46 samsung electronics mdc mdio 0ns min, 300ns max 7 cycles 7 cycles figure 23 mdio sourced by phy input valid 10ns min 10ns min mdc mdio figure 24 mdio sourced by sta timing parameters for utopia, an atm-phy interface specification the ac characteristics are based on the timing specification for the receiver side pof a signal. the setup and hold times are defined with regard to a positive clock edge (see figure 25). tacking the actual used clock frequency into account (e.g. up to the max. frequency), the corresponding (min. and max.) transmit side ? clock to output ? propagation delay specifications can be derived. the timing references (tt5 to tt12) are according to table 8 and 9. clock signal tt5, tt7 tt6, tt8 input setup to clock input hold from clock figure 25 aetup and hold time definition (single- and multi-phy) figure 26 shows the tri-state timing for the multi-phy application (multiple phy devices, multiple output signals are multiplexed together). clock signal tt12 signal going high impedance from clock signal going low impedance to clock tt9 tt11 signal going low impedance from clock tt10 signal going high impedance to clock figure 26 tri-state timing (multi-phy, multiple devices only) in the following tables, a t p (column dir, direction) defines a signal from the atm layer (transmitter, driver) to the phy layer (receiver), a p defines a signal from the phy layer (transmitter, driver) to the atm layer (receiver).
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 47 magic team signal name dir item description min max f1 txclk frequency (nominal) 0 33mhz tt2 txclk duty cycle 40% 60% tt3 txclk peak-to-peak jitter - 5% txclk a t p tt4 txclk rise/fall time - 3ns tt5 input setup to txclk 8ns - txdata[7:0], txprty, txsoc, txenb*, txaddr[4:0] a t p tt6 input hold from txclk 1ns - tt7 input setup to txclk 8ns - tt8 input hold from txclk 1ns - tt9 signal going low impedance to txclk 8ns - tt10 signal going high impedance to txclk 0ns - tt11 signal going low impedance from txclk 1ns - txfull*/txclav[3:0] a p tt12 signal going high impedance from txclk 1ns - table 8 transmit timing (8-bit data bus, n 33mhz at cell interface, multi-phy) signal name dir item description min max f1 rxclk frequency (nominal) 0 33mhz tt2 rxclk duty cycle 40% 60% tt3 rxclk peak-to-peak jitter - 5% rxclk a t p tt4 rxclk rise/fall time - 3ns tt5 input setup to rxclk 8ns - rxenb*, rxaddr[4:0] a t p tt6 input hold from rxclk 1ns - tt7 input setup to rxclk 8ns - tt8 input hold from rxclk 1ns - tt9 signal going low impedance to rxclk 8ns - tt10 signal going high impedance to rxclk 0ns - tt11 signal going low impedance from rxclk 1ns - rxdata[7:0], rxprty, rxsoc, rxempty*/rxclav[3:0] a p tt12 signal going high impedance from rxclk 1ns - table 9 receive timing (8-bit data bus, n 33mhz at cell interface, multi-phy)
s5n8947 (adsl/cable modem mcu) electronics magic team page : 48 samsung electronics 9. package dimension this section describes the mechanical data for the s5n8947 2 08 -pin t qfp package. 208 - t qfp- 2828 package dimensions figure 27 208-tqfp-2828 package dimensions
electronics s5n8947 (adsl/cable modem mcu) samsung electronics page : 49 magic team revision history revision no. date description 0.1 2000 -05-23 S5N8947X (rev.0.1) released. important notice the information furnished by samsung electronics in this document is belived to be accurate and reliable. however, no resposibility is assumed by samsung electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of samsung electronics. samsung electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. for more information tel: (82)-(31)-209-8301, fax: (82)-(31)-209-8309 e-mail: kimil@sec.samsung.com http://www.intl.samsungsemi.com copyright ?2000 samsung electronics, inc. all rights reserved

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